In recent years, in consumer appliances such as a digital home electric appliance, mobile equipment and the like, it is requested to improve a response speed of a switching power supply apparatus and improve performances through a drop in noise so as to supply power in linkage with an operation sequence based on a communication situation. A technique of performance improvement of the switching power supply control apparatus is known (for example, refer to Patent Literature 1).
FIG. 1 is a block diagram showing the configuration of the power supply control apparatus described in the Patent Literature 1. The power supply control apparatus contains a transfer element 161 of a system that includes transfer functions Wry(Z) and WQy(z) in which an equivalent disturbance Q is considered; a transfer element 162 of an inverse system Wm−1(z); and a transfer element 163 as a robust compensator that includes a filter K(z).
A control amount y as an output of the transfer element 161 is drawn out at a node 164 and applied to the transfer element 162. An output from an adder 165 for adding an output of the transfer element 163 and a target value r is added to a different adder 167 via a node 166 and also supplied to the transfer element 161. Also, the adder 167 supplies a difference (subtraction value) between the output of the adder 165, which is branched at the node 166, and the output of the transfer element 162 to the transfer element 163.
FIG. 2 is a block diagram in which the power supply control apparatus shown in FIG. 1 is equivalently converted. With reference to FIG. 2, the power supply control apparatus includes a control target element 154, which satisfies the following state equations when an input h, the control amount y, a first equivalent disturbance qy and a delay ξ are given; a digital controller 170; and an adder 143E:xd(k+1)=Adxd(k)+Bdh(k), andy(k)=Cdxd(k)+qy(k)
Here, xd=[x ξ]T 
The first equivalent disturbance qy is added to an output from the control target element 154 by the adder 143E, and the addition result is outputted as the control amount y.
The digital controller 170 is configured from a combination of transfer elements (from a feedback element 171 to an element 182) having respective parameters of k1, k2, k3, k4, k5, k6, k1r, k2r, k3r, ki, kiz and kin; an element 144A and an element 144F each having an order 1/z (here, z=exp (j ω t)) corresponding to one sample delay; an element 183 of an order 1/z−1 serving as an integrator; an adder 143A; an adder 143B; an adder 184; and an adder 185.
Also, as shown in FIG. 2, the target value r is supplied to a feed forward element 177 for the parameter k1r, a feed forward element 178 for the parameter k2r and a feed forward element 179 for the parameter k3r. Also, the control amount y is supplied to the feedback element 171, the feedback element 172 and the feedback element 176 for the parameter k1, the parameter k2 and the parameter k6.
A calculation delay output ξ1 inside the digital controller 170 is supplied to the feedback element 173 for the parameter k3, and a difference between the target value r and a reference value y is supplied from the adder 184 to the element 183 of the order 1/z−1. Also, a delay output ξ4 from the element 183 of the order 1/z−1 is supplied to the element 182 for the parameter kin.
An output from the element 182 for the parameter kin and outputs from the respective feedback elements 175, 176 for the parameters k5, k6 and an output from the feed forward element 179 for the parameter k3r are respectively added by the second adder 185.
An addition output from this second adder 185 is supplied to the first element 144F of the order 1/z, and the delay output ξ3 from the first element 144F of the order 1/z is supplied to the feedback element 175 for the parameter k5 and the elements 180 and 181 for the parameters ki and kix, respectively.
An output from the element 180 for the parameter ki, outputs from the respective feedback elements 171, 173 and 174 for the parameters k1, k3 and k4, an output from the feed forward element 178 for the parameter k2r, and a second equivalent disturbance qv are added by the third adder 143A.
An addition output v from the third adder 143A is supplied to the second element 144A of the order 1/z. Then, a delay output ξ2 from the second element 144A of the order 1/z, an output from the feedback element 172 for the parameter k2, an output from the feed forward element 177 for the parameter k1r and an output from the element 181 for the parameter kiz are added by the fourth adder 143B. The delay output ξ2 from the second element 144A of the order 1/z as mentioned above is supplied to the feedback element 174 for the parameter k4, and an addition output h from the fourth adder 143B is given to the control target element 154.
In other words, a control system of the power supply control apparatus configured from the digital controller shown in FIG. 2 includes a first feedback element for outputting a product of the control amount y and the parameter k1, a second feedback element for outputting a product of the control amount y and the parameter k2, a third feedback element for outputting a product of the first delay output ξ1 and the parameter k3, a fourth feedback element for outputting a product of the second delay output ξ2 and the parameter k4, a fifth feedback element for outputting a product of the third delay output ξ3 and the parameter k5, and a sixth feedback element for outputting a product of the control amount y and the parameter k6.
Also, the control system includes a first calculating element for calculating a difference between the control amount y and the target value r; an integrating element for integrating a calculation value from the first calculating element to convert into a fourth delay output ξ4; a first accumulating element for outputting a product of the fourth delay output ξ4 from the integrating element and a parameter kin; a first adding element for adding an output from the first accumulating element, an output from the fifth feedback element and an output from the sixth feedback element; a first delaying element for defining the addition result from the first adding element as the third delay output ξ3 that is sampling-delayed; a second accumulating element for outputting a product of the third delay output ξ3 and the parameter ki; and a third accumulating element for outputting a product of the third delay output ξ3 and the parameter kiz.
Then, the control system includes a second adding element for adding the second equivalent disturbance qv, the output from the second accumulating element, the output from the first feedback element, the output from the third feedback element, and the output from the fourth feedback element; a second delaying element for defining the addition result from the second adding element as the second delay output ξ2 that is sampling-delayed; and a third adding element for adding the output of the second delaying element, the output of the third accumulating element and the output of the second feedback element to generate an input h to the control target.
Here, the adder 143A corresponds to the first adding element and the second adding element, the adder 143B corresponds to the second adding element and the third adding element, the element 144A corresponds to the second delaying element, and the element 144F corresponds to the first delaying element and the delaying element. Also, the control target element 154 corresponds to the control target, the feedback element 171 corresponds to the first feedback element, the feedback element 172 corresponds to the second feedback element, the feedback element 173 corresponds to the third feedback element, the feedback element 174 corresponds to the fourth feedback element, the feedback element 175 corresponds to the fifth feedback element, and the feedback element 176 corresponds to the sixth feedback element. Also, the feed forward element 177 corresponds to the first feedback element, the feedback element 178 corresponds to the second feed forward element, and the feed forward element 179 corresponds to the third feed forward element. Also, the element 80 corresponds to the second accumulating element, the element 82 corresponds to the first accumulating element, the element 83 corresponds to the integrating element, the first adder 84 corresponds to the first calculating element, the second adder 85 corresponds to the first adding element, and the first adder 87 corresponds to the first calculating element.